The present invention relates to a digital-analog conversion circuit which converts a digital signal to an analog signal.
In portable devices such as portable telephones, the digital-analog conversion circuit is integrated in a semiconductor integrated circuit such as a radio IC. In recent years, as the process of integrated circuits have become finer. As a consequence, power supply voltage which is used in the integrated circuits has also lowered. Therefore, digital-analog circuits which can work at a low power supply voltage are in demand.
Digital-analog conversion circuits obtained by combining a resistor string digital-analog converter and weighted resistors are known (See for example, Japanese Patent Application Laid-Open Publication No. 62-227224). FIG. 1 is a diagram showing a conventional digital-analog conversion circuit (for 8 bits) disclosed in Japanese Patent Application Laid-Open Publication No. 62-227224.
This digital-analog conversion circuit includes a resistor string digital-analog conversion section 11 and a binary weighting circuit 12 having resistor groups which consist of weighted value resistors and switch groups which is connected to the weighted value resistors. The digital-analog conversion section 11 receives n high-order bits (for example, D4, . . . , D7) of an input digital value, and outputs an analog voltage corresponding thereto.
A resistor group and a switch group of the binary weighting circuit 12 are inserted between a positive power supply side of a resistor string included in the digital-analog conversion section 11 and a positive power supply (Vr(+)). A resistor group and a switch group of the binary weighting circuit 12 are inserted also between a negative power supply side of the resistor string and a negative power supply (Vr(xe2x88x92)). Each of the weighted value resistors of the resistor group is inserted or removed by a switch group. Switches S11 to S14 and S21 to S24 of the switch groups are, for example, MOS transistors.
The binary weighting circuit 12 receives m low-order bits (for example, D0, . . . , D3) of the input digital value. According to insertion and removal of the weighted value resistors conducted by the switch groups, the binary weighting circuit 12 outputs a potential obtained by dividing a voltage corresponding to one step of the digital-analog conversion section 11 by xc2xdm. In the digital-analog conversion circuit shown in FIG. 1, therefore, 2m+n steps are obtained.
In the above described conventional digital-analog conversion circuit, the switch groups of the binary weighting circuit 12 are connected in series with the resistor string included in the digital-analog conversion section 11. A voltage variation corresponding to low-order bits of the input digital value is adjusted by switching over the switches S11 to S14 and S21 to S24 of the switch groups. Therefore, the conversion precision of this digital-analog conversion circuit is influenced by on-resistance values of the switches S11 to S14 and S21 to S24.
Therefore, there is a problem that the circuit area needs to be increased for activating the above described conventional digital-analog conversion circuit at a low power supply voltage. The reason is as follows. If the power supply voltage becomes low, the voltage of a control signal for turning gates of MOS transistors forming the switches on is lowered. For suppressing the maximum on-resistance to such a level as not to exert a serious influence on the digital-analog conversion precision, therefore, the gate area must be increased.
It is an object of the present invention to provide a digital-analog conversion circuit capable of suppressing an increase of the circuit area even in the case where it is activated with a low power supply voltage.
The-digital-analog conversion circuit according to the present invention has such a configuration that a potential at an arbitrary node in the resistor string is changed by changing potentials of both ends while keeping a potential difference across the resistor string constant.
FIG. 2 is a circuit diagram which describes the principle of a digital-analog conversion circuit according to the present invention. This digital-analog conversion circuit includes resistor strings RS1, RS2 and RS3, a first controller (controller 1) 21, a second controller (controller 2) 22, a switch group SW, a first variable voltage source VH, a second variable voltage source VL, a buffer 23, input terminals 24 and 25, and an output terminal 26. Legends N1, N2, N3, N4 and N5 denote nodes, respectively.
The first resistor string RS1 is connected in series between the node N1 and the node N2. The second resistor string RS2 is connected in series between the node N3 and the node N4. The third resistor string RS3 is connected in series between the node N2 and the node N3. Therefore, the three resistor strings RS1, RS2 and RS3 are connected in series.
The first input terminal 24 is supplied with m high-order bits (for example, Dn+mxe2x88x921, . . . , Dn+1, Dn) of an input digital signal. The second input terminal 25 is supplied with n low-order bits (for example, Dnxe2x88x921, . . . , D1, D0) of the input digital signal.
The first controller 21 controls switchover of the switch group SW according to the m high-order bits of the input signal. The resistor strings RS1, RS2, and RS3, the first controller 21, and the switch group SW form a digital-analog conversion circuit of resistor string type. By using the digital-analog conversion circuit of resistor string type, an analog output corresponding to m high-order bits of the input digital signal is obtained.
The second controller 22 controls potentials of two variable voltage sources VH and VL so as to make the potential difference between the node N1 and the node N4 always constant. Here, the first variable voltage source VH applies a potential of a relatively high level to the node N1. The second variable voltage source VL applies a potential of a relatively low level to the node N4.
As a result of variation of the potentials of the two variable voltage sources VH and VL controlled by the second controller 22, an analog output corresponding to the n low-order bits of the input digital signal is obtained. The analog signal corresponding to the input digital signal is outputted to the output terminal 26 through the node N5 and the buffer 23.
FIG. 3 is a circuit diagram showing the principle of the digital-analog conversion circuit according to the present invention in more detail. FIG. 3 shows in more detail the variable voltage sources VH and VL of the digital-analog conversion circuit shown in FIG. 2. In this figure, components that are common to those in FIG. 2 are provided like legends and description thereof is omitted.
In the example shown in FIG. 3, the variable voltage source VH (see FIG. 2) includes a first constant-voltage source VRH, a second constant voltage source VRHH, a first differential amplifier 27, a first transistor Tr1, and a first switch group S1. The first transistor Tr1 is connected between the node N1 and the first constant voltage source VRH. The first transistor Tr1 operates on the basis of an output signal of the first differential amplifier 27.
One input terminal of the first differential amplifier 27 is connected to the second constant voltage source VRHH. The other input terminal of the first differential amplifier 27 is connected to a suitable place of the first resistor string RS1 through the first switch group S1. Switchover operation of the first switch group S1 is controlled by the second controller 22.
N7 is a node connected to the first resistor string RS1 via the first switch group S1. A potential at the node N7 is subjected to feedback control by the first differential amplifier 27 so as to be equal to a potential at the second constant voltage source VRHH by a norator action of the first transistor Tr1.
In the example shown in FIG. 3, the variable voltage source VL (see FIG. 2) includes a third constant voltage source VRL, a fourth constant voltage source VRLL, a second differential amplifier 28, a second transistor Tr2, and a second switch group S2. The second transistor Tr2 is connected between the node N4 and the third constant voltage source VRL. The second transistor Tr2 operates on the basis of an output signal of the second differential amplifier 28.
One input terminal of the second differential amplifier 28 is connected to the fourth constant voltage source VRLL. The other input terminal of the second differential amplifier 28 is connected to a suitable place of the second resistor string RS2 through the second switch group S2. Switchover operation of the second switch group S2 is controlled by the second controller 22.
N8 is a node connected to the second resistor string RS2 via the second switch group S2. A potential at the node N8 is subjected to feedback control by the second differential amplifier 28 so as to become equal to a potential at the fourth constant voltage source VRLL by a norator action of the second transistor Tr2.
Owing to such a configuration, a potential difference between the suitable node of the first resistor string RS1 connected to the node N7 by the first switch group S1 and the suitable node of the second resistor string RS2 connected to the node N8 by the second switch group S2 always becomes a constant value V7-8.
Here, the second controller 22 has such a configuration as to control the switchover operation of the first and second switch groups S1 and S2 in order that the resistance between the suitable node of the first resistor string RS1 connected to the node N7 and the suitable node of the second resistor string RS2 connected to the node N8 always becomes a constant value R7-8.
Therefore, a current I flowing through the three resistor strings RS1, RS2 and RS3 connected in series always becomes a constant value, and it is represented by the following equation 1.
I=V7-8/R7-8xe2x80x83xe2x80x83(1)
Furthermore, assuming that the resistance between the node N1 and the node N4 located at both ends of the three resistor strings RS1, RS2 and RS3 is R1-4, the potential difference V1-4 between the node N1 and the node N4 always becomes a constant value, and it is represented by the following equation 2.
V1-4=V7-8xc3x97R1-4/R7-8xe2x80x83xe2x80x83(2)
In the digital-analog conversion circuit shown in FIG. 3, the potential of the node N1 and the potential of the node N4 can be changed by the above described action while keeping the potential difference between ends (node N1 and node N4) of the resistor strings RS1, RS2 and RS3 constant.
By using the resistor string digital-analog conversion circuit including the resistor strings RS1, RS2 and RS3, the first controller 21, and the switch group SW, an analog output corresponding to the m high-order bits of the input digital signal is obtained. Furthermore, an analog output corresponding to the n low-order bits of the input digital signal is determined by changes of the potential of the node N1 and the potential of the node N4.
According to the present invention, therefore, it is not necessary to provide a switch group for obtaining the analog output corresponding to the n low-order bits of the input digital signal in series to the resistor string, unlike the conventional technique. Therefore, an increase of the circuit area which poses a problem in the case where the conventional digital-analog conversion circuit is activated with a low power supply voltage can be suppressed.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.